Invalid entry - mmu page tables

Hi, I'm pretty much new to this. I have Level 2 table (for ARMv8 - 64KB granule) with multiple 512MB block entries inside. Some of those blocks are not valid (belong to the reserved/not accessible memory...
Invalid entry - mmu page tables

Hi, I'm pretty much new to this. I have Level 2 table (for ARMv8 - 64KB granule) with multiple 512MB block entries inside. Some of those blocks are not valid (belong to the reserved/not accessible memory...
MMU page table linking with relative addressing

To my understanding the page tables entries that point to the next page table need to be absolute addresses, so from 0x0. Now I would like to generate my page tables before runtime and cannot know the...
Enable and disable MMU page table caching in L2

Hello, I am using a dual core Cortex A9 CPU and I want to enable MMU caching in L2. By default all the DDR memory region is set as non-cacheable. But then I want only the DDR regions allocated...
Enable and disable MMU page table caching in L2

Hello, I am using a dual core Cortex A9 CPU and I want to enable MMU caching in L2. By default all the DDR memory region is set as non-cacheable. But then I want only the DDR regions allocated...