ARMv7-A: Cache maintenance operation by VA, performance

Hi, according to this talk , cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop...
ARMv7-A: Cache maintenance operation by VA, performance

Hi, according to this talk , cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop...
Can multiple cores perform L2 cache maintenance operations to flush (say) different addresses from the L2 cache.

I am concerned about a situation where code running on one processor core is writing to L2 cache register(s) to flush (Clean and Invalidate Line by Physical Address operation) one address from the L2...
Can multiple cores perform L2 cache maintenance operations to flush (say) different addresses from the L2 cache.

I am concerned about a situation where code running on one processor core is writing to L2 cache register(s) to flush (Clean and Invalidate Line by Physical Address operation) one address from the L2...
cache maintenance on cortex-a8

Note: This was originally posted on 17th November 2011 at http://forums.arm.com [size=2]Hi ARM experts, I am a little confused about the cache maintenance on cortex-a8. Some understanding were listed...