• What flow should I execute to make cache and MMU work properly when I turn into non secure world?
    In A7 platform with TZ extension , I know that there is a virtual MMU for non secure world, and I think it should be enabled after entering non secure world. But the most confusing thing is that what...
  • What flow should I execute to make cache and MMU work properly when I turn into non secure world?
    In A7 platform with TZ extension , I know that there is a virtual MMU for non secure world, and I think it should be enabled after entering non secure world. But the most confusing thing is that what...
  • ARM Bootloader: flush D/I-cache, disable D-cache and enable I-cache
    Hello everyone, I'm analysing u-boot for s3c2440(arm920t), and at the first stage u-boot does something like this: mov R0, #0 mcr P15, 0, R0, C7, C7, 0   ; flush v3/v4 caches mcr P15, 0, R0, C8...
  • ARM Bootloader: flush D/I-cache, disable D-cache and enable I-cache
    Hello everyone, I'm analysing u-boot for s3c2440(arm920t), and at the first stage u-boot does something like this: mov R0, #0 mcr P15, 0, R0, C7, C7, 0   ; flush v3/v4 caches mcr P15, 0, R0, C8...
  • Load / Store timings with different cache settings
    Hello, I am timing load and store instructions for baremetal program by stepping though execution using OpenOCD and using the PMU cycle counter with single cycle granularity. I am running the program...