GIC-v3: control of group 0 interrupts activation and selection

Hi, I have two main questions, about the handling of group 0 interrupts: from my understanding of the GIC-v3 documentation, any secure OS (EL1, SCR.NS == 0) has access to ICC_IGRPEN0_EL1: Am I correct...
GIC-v3: control of group 0 interrupts activation and selection

Hi, I have two main questions, about the handling of group 0 interrupts: from my understanding of the GIC-v3 documentation, any secure OS (EL1, SCR.NS == 0) has access to ICC_IGRPEN0_EL1: Am I correct...
GIC 3.0's SGI interrupt latency seems much bigger than GIC 2.0

Hi, I tested SGI interrupt latency, it seems that GIC3.0's SGI interrupt latency are much bigger than GIC2.0. How to test: GIC3.0: 1. read timestamp(t01) 2. core0 write ICC_SGI0R_EL1 to trigger...
GIC 3.0's SGI interrupt latency seems much bigger than GIC 2.0

Hi, I tested SGI interrupt latency, it seems that GIC3.0's SGI interrupt latency are much bigger than GIC2.0. How to test: GIC3.0: 1. read timestamp(t01) 2. core0 write ICC_SGI0R_EL1 to trigger...
GIC IAR always returns spurious interrupt

Note: This was originally posted on 29th March 2012 at http://forums.arm.com Trying to write a GIC driver (V1 w/security extensions) on an embedded A9 MPCORE based system with 2 cores. Can successfully...