L2C-310 Cache Sync

Hi, I’m a little bit confused regarding the atomic operation Cache Sync (REG7_CACHE_SYNC). How should the maintenance operation used? I have seen an example in XILINX SDK. void Xil_L2CacheFlush...
L2C-310 Cache Sync

Hi, I’m a little bit confused regarding the atomic operation Cache Sync (REG7_CACHE_SYNC). How should the maintenance operation used? I have seen an example in XILINX SDK. void Xil_L2CacheFlush...
L2C-310 double linefill issuing

Hi, I have a problem to understand the functionality of double linefill issuing. In which case the cache controller loads a second cache line from L3 into L2? Where is the difference to prefetch?...
L2C-310 double linefill issuing

Hi, I have a problem to understand the functionality of double linefill issuing. In which case the cache controller loads a second cache line from L3 into L2? Where is the difference to prefetch?...
ARM Cortex-A9 Preload and Lock Code in L2C-310

I've been studying and experimenting with the caches on an ARM Cortex-A9, namely a Zynq SoC, for the past week with the main objective of loading and locking part of my code to L2 (PL310). The steps I...