AXI interconnect performance improvement

Hi all, I am working on a SOC using Xilinx ZYNQ US+ FPGAs. I am transferring data to DDR4 memory by AXI interconnect cores. I am going to find a way to improve the performance of my interconnect. I...
AXI Interconnect PL301 r2p3

I have an AXI master and an AXI slave connected to interconnect in my setup. I have used AMBA Designer tool to generate Interconnect RTL. I have a question on Tidemark : What is the significance...
AXI interconnect performance improvement

Hi all, I am working on a SOC using Xilinx ZYNQ US+ FPGAs. I am transferring data to DDR4 memory by AXI interconnect cores. I am going to find a way to improve the performance of my interconnect. I...
AXI Interconnect PL301 r2p3

I have an AXI master and an AXI slave connected to interconnect in my setup. I have used AMBA Designer tool to generate Interconnect RTL. I have a question on Tidemark : What is the significance...
AXI ID problem for cascaded interconnect design

Note: This was originally posted on 18th December 2010 at http://forums.arm.com As we know, the interconnect can add bits to ID fields to indentify the master issuing the transaction. In the SoC design...