• Question about T3 and T4 encoding of B/Bcc (Branch) Instruction
    On Cortex v7M architecture, looking at the T3 and T4 encodings for the B and Bcc instructions in the architecture reference manual... Do T3 and T4 really have the J bits of the immediate value in the...
  • Question about T3 and T4 encoding of B/Bcc (Branch) Instruction
    On Cortex v7M architecture, looking at the T3 and T4 encodings for the B and Bcc instructions in the architecture reference manual... Do T3 and T4 really have the J bits of the immediate value in the...
  • For the thumb branch instruction (b), arm-none-eabi-gcc uses both T1 and T2 encodings, it is legal?
    Hello, I just found arm-gcc uses both two thumb encodings, see the following example ```C int x = 100, y = 60; if (x - 30 > y + 11) { x = 0xefff; } else { y = 0xdffff; } /* arm-none-eabi-gcc...
  • How do branch instructions influence the performance of Cortex-A77?
    In "Arm Cortex-A77 Core Software Optimization Guide", it says: In my understanding, it would be very difficult to predict multiple branch instructions in a 32-Byte aligned instruction memory...
  • How do branch instructions influence the performance of Cortex-A77?
    In "Arm Cortex-A77 Core Software Optimization Guide", it says: In my understanding, it would be very difficult to predict multiple branch instructions in a 32-Byte aligned instruction memory...