Cortex-A8/A15 L1 cache

Hi, I would like to know whether the cortex-A8/A15 L1cache has ECC or parity check for error checking, or not. I know L2 cache has ECC function. Bur I don't know about L1 cache. Please let me know. Best...
Cortex-A8/A15 L1 cache

Hi, I would like to know whether the cortex-A8/A15 L1cache has ECC or parity check for error checking, or not. I know L2 cache has ECC function. Bur I don't know about L1 cache. Please let me know. Best...
Cortex a15 disable non-blocking cache

Hi, I'm working on ARM Cortex-A15. Is possible to disable the non-blocking cache behavior? Is possible to set the in-order execution? Thanks in advance for the help. Regards Paolo.
Cortex a15 disable non-blocking cache

Hi, I'm working on ARM Cortex-A15. Is possible to disable the non-blocking cache behavior? Is possible to set the in-order execution? Thanks in advance for the help. Regards Paolo.
Cortex-A15 Cache Maintenance DCIMVAC vs DCCIMVAC

I am trying to understand the difference between the DCIMVAC and DCCIMVAC cache maintenance operations in the Cortex-A15 architecture. I have run some tests on a TI AM5718 SOC that features a single-core...