shareable domain and cache policy problem

Hi, I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE...
shareable domain and cache policy problem

Hi, I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE...
Cortex A53 : Cache policy setting

Hi, Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? I'm enabling the caching using the SCTRL register...
Cortex A53 : Cache policy setting

Hi, Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? I'm enabling the caching using the SCTRL register...
shareability memory attribute

Hi ARM experts, For shareability attribute, have some confusions: 1 For a memory location with cacheability attribute, does hardware do "flush" action after "writing" to push data to end if shareability...