• Ignored bits in ARMv7a LPAE / ARMv8 Table descriptors
    Hi ! Let's first consider ARMv8 aarch64 VMSA and stage 1 Table descriptors. I can read in the ARM ARM in 'Next-level attributes in stage 1 VMSAv8-64 Table descriptors' that bits [58:52] are Ignored...
  • Ignored bits in ARMv7a LPAE / ARMv8 Table descriptors
    Hi ! Let's first consider ARMv8 aarch64 VMSA and stage 1 Table descriptors. I can read in the ARM ARM in 'Next-level attributes in stage 1 VMSAv8-64 Table descriptors' that bits [58:52] are Ignored...
  • how to understand ARMv8 exception level1 secure/non-secure MMU?
    Hi Experts ,      ARMv8 MMU TTBRn_ELx registers are banked by exception level.      In "DDI0487A_b_armv8_arm.pdf" page 1640, the controlling register of secure EL1&0 stage1 is TTBR0_EL1      and Non-secure...
  • how to understand ARMv8 exception level1 secure/non-secure MMU?
    Hi Experts ,      ARMv8 MMU TTBRn_ELx registers are banked by exception level.      In "DDI0487A_b_armv8_arm.pdf" page 1640, the controlling register of secure EL1&0 stage1 is TTBR0_EL1      and Non-secure...
  • Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"?
    I've gotten virtual memory working on ARMv8 after crafting the page tables. Oddly, _most_ of my translations are working (identity mapped) save for Flash which sits at physical address zero. I use a single...