• Trace decompressor: Are barrier instructions and synchronization primitives really waypoints?
    Dear all, System: Altera Cyclone V with ARM Cortex-A9 dual-core MPU. CoreSight PFT 1.0 I am currently developing a trace decompressor. I wrote a function that parses the program image in order to...
  • Trace decompressor: Are barrier instructions and synchronization primitives really waypoints?
    Dear all, System: Altera Cyclone V with ARM Cortex-A9 dual-core MPU. CoreSight PFT 1.0 I am currently developing a trace decompressor. I wrote a function that parses the program image in order to...
  • Is any synchronization barrier instruction necessary after writing SPSel to switch to SP0 on armv8?
    Hi Fellows, I want to switch stack pointer to SP0 from SP1 every time an exception is taken to EL1 on armv8. I execute MSR SPSel, #0 to do this. My question is that is it necessary to use an ISB intruction...
  • Is any synchronization barrier instruction necessary after writing SPSel to switch to SP0 on armv8?
    Hi Fellows, I want to switch stack pointer to SP0 from SP1 every time an exception is taken to EL1 on armv8. I execute MSR SPSel, #0 to do this. My question is that is it necessary to use an ISB intruction...
  • Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?
    Hi Experts, I'm reading white paper for ARMv7 and ARMv8. but when i reading cache part and memory re-ordering, i have silly questions..... Suppose there are below instructions..   Core A:      STR R0...