how to enable am335x Monitor debug-mode

Hi , The monitor debug mode can be configured in DSCR, which is writable via APB interface for am335x. But, I read the DRAR(MRC p14, 0, <Rd>, c1, c0, 0) and DSAR(MRC p14, 0, <Rd>, c2, c0, 0). Both of...
how to enable am335x Monitor debug-mode

Hi , The monitor debug mode can be configured in DSCR, which is writable via APB interface for am335x. But, I read the DRAR(MRC p14, 0, <Rd>, c1, c0, 0) and DSAR(MRC p14, 0, <Rd>, c2, c0, 0). Both of...
Performance monitor event numbers in Tegra2 (Cortex-A9 MPCore)

Note: This was originally posted on 16th July 2010 at http://forums.arm.com I am trying to collect some data on a Tegra2 using the performance monitors. I have a question about some of the event numbers...
Performance monitor event numbers in Tegra2 (Cortex-A9 MPCore)

Note: This was originally posted on 16th July 2010 at http://forums.arm.com I am trying to collect some data on a Tegra2 using the performance monitors. I have a question about some of the event numbers...
ARM-A15 SoC integration for Simulation (VCS) How to Enable traces for debug

Hi, I owe ARM-A15 integration and verification to our SoC simulation using VCS tools. I have no visibility or any way to track down the ARM Program counter for debug. Is there any ARM verification...