Cortex-A53 direct access to cache: How are instructions encoded in the L1 I-cache?

The TRM for the Cortex-A53 has a section on direct access to various internal memories, including the L1 I-cache and D-caches. I'm successfully able to dump both tag and data for the I-cache and D-cache...
Cortex-A53 direct access to cache: How are instructions encoded in the L1 I-cache?

The TRM for the Cortex-A53 has a section on direct access to various internal memories, including the L1 I-cache and D-caches. I'm successfully able to dump both tag and data for the I-cache and D-cache...
Which ARMv8 register controls cache partitioning

Hi ARM folks, Which register controls the cache partitioning behavior on ARMv8 chips? My group is working with a Cavium ThunderX, and we're trying to experiment with different cache partitioning...
Which ARMv8 register controls cache partitioning

Hi ARM folks, Which register controls the cache partitioning behavior on ARMv8 chips? My group is working with a Cavium ThunderX, and we're trying to experiment with different cache partitioning...
On Cortex-M7, can speculative access bring accessed data to D cache?

Asking this to better understand how to manage cache consistency on I/O buffer for DMA read. Is it possible that in between of cache invalidation on the buffer and end of DMA read, a speculative data...