A8: Keeping Cache-enabled and MMU-disabled

Hi all, A Question about the A8 processor. If I enable the L1 and L2 caches, I see a performance boost even if the MMU is disabled. I was under the impression that the MMU is required to be enabled...
A8: Keeping Cache-enabled and MMU-disabled

Hi all, A Question about the A8 processor. If I enable the L1 and L2 caches, I see a performance boost even if the MMU is disabled. I was under the impression that the MMU is required to be enabled...
Enable and disable MMU page table caching in L2

Hello, I am using a dual core Cortex A9 CPU and I want to enable MMU caching in L2. By default all the DDR memory region is set as non-cacheable. But then I want only the DDR regions allocated...
Enable and disable MMU page table caching in L2

Hello, I am using a dual core Cortex A9 CPU and I want to enable MMU caching in L2. By default all the DDR memory region is set as non-cacheable. But then I want only the DDR regions allocated...
Can I enable and use D-Cache with disabled MMU?

Dear experts, I can't find any information whether d-cache could be used in ARMv8-A with disabled MMU. I found smth here - http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka8788.html...