Cortex-A8/A15 L1 cache

Hi, I would like to know whether the cortex-A8/A15 L1cache has ECC or parity check for error checking, or not. I know L2 cache has ECC function. Bur I don't know about L1 cache. Please let me know. Best...
Cortex-A8/A15 L1 cache

Hi, I would like to know whether the cortex-A8/A15 L1cache has ECC or parity check for error checking, or not. I know L2 cache has ECC function. Bur I don't know about L1 cache. Please let me know. Best...
Cortex-A9/A15 L1 d-cache architecture

Note: This was originally posted on 21st March 2012 at http://forums.arm.com Dear friends, I'm a PhD candidate at the Complutense University of Madrid. I'm doing reasearch on memory allocation over the...
Cortex-A15 Cache Maintenance DCIMVAC vs DCCIMVAC

I am trying to understand the difference between the DCIMVAC and DCCIMVAC cache maintenance operations in the Cortex-A15 architecture. I have run some tests on a TI AM5718 SOC that features a single-core...
Cortex-A15 Cache Maintenance DCIMVAC vs DCCIMVAC

I am trying to understand the difference between the DCIMVAC and DCCIMVAC cache maintenance operations in the Cortex-A15 architecture. I have run some tests on a TI AM5718 SOC that features a single-core...