Trace decompressor: Are barrier instructions and synchronization primitives really waypoints?

Dear all, System: Altera Cyclone V with ARM Cortex-A9 dual-core MPU. CoreSight PFT 1.0 I am currently developing a trace decompressor. I wrote a function that parses the program image in order to...
Trace decompressor: Are barrier instructions and synchronization primitives really waypoints?

Dear all, System: Altera Cyclone V with ARM Cortex-A9 dual-core MPU. CoreSight PFT 1.0 I am currently developing a trace decompressor. I wrote a function that parses the program image in order to...
Data synchronization Barrier and cache.

Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before...
Data synchronization Barrier and cache.

Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before...
Difference between SP_EL1 and SPSEL + MOV

Let's say that I'm running in EL1 and I want to change the stack location used by the exception code. Using the SP_EL1 register is actually not permitted when running in EL1, so something like this...