• Does CCI-400 guarantees cache coherency between secure and non-secure worlds?
    Hi Experts, I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC. While multi-core testing, I'm facing some wired problem on my world shared memory mechanism. When I run world shared memory...
  • Does CCI-400 guarantees cache coherency between secure and non-secure worlds?
    Hi Experts, I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC. While multi-core testing, I'm facing some wired problem on my world shared memory mechanism. When I run world shared memory...
  • How to do from Secure(EL3) to Non-secure Exception level transition in ARMV8-A ?
    Hi all i trying do transition from EL3 to EL2 exception ,but after ERET of EL3 mode it change the mode to EL2 , but as soon as when it will execute first instruction of EL2 , then It goes to Exception...
  • How to do from Secure(EL3) to Non-secure Exception level transition in ARMV8-A ?
    Hi all i trying do transition from EL3 to EL2 exception ,but after ERET of EL3 mode it change the mode to EL2 , but as soon as when it will execute first instruction of EL2 , then It goes to Exception...
  • Interrupts from the secure world to the non-secure world.
    Hello experts, I am using SAM L11 (Core is Cortex-M23). I did a simple test of the interrupt. In the case of the handler was the secure world, it worked as I expected. The instruction sequences are...