PMU's cycles counter showing unstable values

I'm trying to measure performance of my code by using pmu. Code placed in EL1. To test pmu I created simple loop of couple operations. I did it under spinlock with disabled interrupts to prevent any preemption...
PMU's cycles counter showing unstable values

I'm trying to measure performance of my code by using pmu. Code placed in EL1. To test pmu I created simple loop of couple operations. I did it under spinlock with disabled interrupts to prevent any preemption...
Cortex-A9 PMU cycle counter not always incrementing at CPU frequency?

Hello, I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU...
Cortex-A9 PMU cycle counter not always incrementing at CPU frequency?

Hello, I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU...
Cortex-R4 PMU CP15 cycle counter value : runto readout vs step by step to readout..

Looking at this cycle counter value, and as they say starring at it with blank mind .. not understanding it. Very seems trivial setup: I just enable it early at startup, just after my PLL's all set...