• ACE - ReadNoSnoop transaction
    In ACE Specifications - ARM IHI 0022E, in ReadNoSnoop transactions how is the following other state of cacheline given on page number C4-197 transaction permitted : Start State  - ShareClean RRESP[3]...
  • ACE - ReadNoSnoop transaction
    In ACE Specifications - ARM IHI 0022E, in ReadNoSnoop transactions how is the following other state of cacheline given on page number C4-197 transaction permitted : Start State  - ShareClean RRESP[3]...
  • In CHI spec, if the Requester initial state is UD or SD, what the final cache state of a ReadClean transaction should be?
    In CHI specification, Table 4-33 shows that the Requester final cache state of a ReadClean transaction is UD/SD while its initial state is UD/SD/UDP. But in Table 4-5, it seems that only UC/SC state...
  • Does ReadNoSnpSep in IHI0050C version of CHI protocol applicable only with DMT or was it applicable in non DMT case too? In IHI0050E it is applicable in both DMT and non DMT transactions, need to know...
    Does ReadNoSnpSep in IHI0050C version of CHI protocol applicable only with DMT or was it applicable in non DMT case too? In IHI0050E it is applicable in both DMT and non DMT transactions, need to know...
  • AXI 4 protocol - can read transaction and write transaction occur at the same time?
    AXI 4 protocol - can read transaction and write transaction occur at the same time? In addition can 2 or more wrirte transacation occur at the same time?