Endian about AHB-Lite and AHB5 Specification

Hello to all, I have a question about AMBA3 AHB-Lite and AHB5 Specification: In AMBA3 AHB-Lite Specification, " Table 6-2 Active byte lanes for a 32-bit big-endian data bus" is mean word-invariant...
Endian about AHB-Lite and AHB5 Specification

Hello to all, I have a question about AMBA3 AHB-Lite and AHB5 Specification: In AMBA3 AHB-Lite Specification, " Table 6-2 Active byte lanes for a 32-bit big-endian data bus" is mean word-invariant...
AMBA AHB5 to AHB lite

Hello, what are the additional features added or removed in AHB lite; regards Pavan
AMBA AHB5 to AHB lite

Hello, what are the additional features added or removed in AHB lite; regards Pavan
Protection Control Bits of DMA Controller

Can someone shed some light on how bufferable and cacheable features work in ARM9 DMA controller? An example would be much appreciated. What are the differences between them?