Does the Arm Cortex-52+ support multi-core / cache coherent / SMP configurations?

The Arm Cortex-R Comparison Table downloaded from Arm ( https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwibler1ifX5AhWOXvEDHY-QAwkQFnoECBIQAQ&url=https%3A%2F%2Fwww.arm.com%2F...
Cortex-R5 r1p2: Data/Instruction Cache - Configuration during startup, run-time? Specific considerations using RTOS, DMA?

Hello, On an exising project based on Cortex-R5, with a limited ATCM/BTCM resources, we need to start using Data/Instruction Cache with DDR (DRAM), to improve performance. There is a lot scattered...
Cortex-R5 r1p2: Data/Instruction Cache - Configuration during startup, run-time? Specific considerations using RTOS, DMA?

Hello, On an exising project based on Cortex-R5, with a limited ATCM/BTCM resources, we need to start using Data/Instruction Cache with DDR (DRAM), to improve performance. There is a lot scattered...
L2 cache configuration

Note: This was originally posted on 20th April 2011 at http://forums.arm.com Hello guys, Anybody here knows what is default size of ARM Cortex-A8 L2 cache as it is given in the manual that...
L2 cache configuration

Note: This was originally posted on 20th April 2011 at http://forums.arm.com Hello guys, Anybody here knows what is default size of ARM Cortex-A8 L2 cache as it is given in the manual that...