• Does the Arm Cortex-52+ support multi-core / cache coherent / SMP configurations?
    The Arm Cortex-R Comparison Table downloaded from Arm ( https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&ved=2ahUKEwibler1ifX5AhWOXvEDHY-QAwkQFnoECBIQAQ&url=https%3A%2F%2Fwww.arm.com%2F...
  • Multi-core scripting
    Our ASIC has 4 independent M7 cores (it's not a quad core configuration). In DS-5, we created one Debug Configuration per core to download the correct fw image to each core. We would like to write a...
  • multi core programming
    hi I have four functions and I am using cortex a7 processor. I want every core to execute one function. so to achieve this which registers and which manual and section should I refer too. i have placed...
  • Multi-core scripting
    Our ASIC has 4 independent M7 cores (it's not a quad core configuration). In DS-5, we created one Debug Configuration per core to download the correct fw image to each core. We would like to write a...
  • multi core programming
    hi I have four functions and I am using cortex a7 processor. I want every core to execute one function. so to achieve this which registers and which manual and section should I refer too. i have placed...