making physical memory pages not cacheable (probabaly by modifying page table entry)

I need to make physical memory pages uncacheable, it seems that in armv7 (I am using arm cortex A9) there are some bits that determine the memory type. we have two level translations (so we have pgd and...
making physical memory pages not cacheable (probabaly by modifying page table entry)

I need to make physical memory pages uncacheable, it seems that in armv7 (I am using arm cortex A9) there are some bits that determine the memory type. we have two level translations (so we have pgd and...
aarch64 kernel using aarch32 page tables

Hi ! I'm trying to update my custom kernel, working with short or long descriptor in armv7a to a target supporting armv8. My current setup uses TTBR0 to point to the PL0 page table and TTBR1 to point...
aarch64 kernel using aarch32 page tables

Hi ! I'm trying to update my custom kernel, working with short or long descriptor in armv7a to a target supporting armv8. My current setup uses TTBR0 to point to the PL0 page table and TTBR1 to point...
mmu page table

Note: This was originally posted on 22nd April 2013 at http://forums.arm.com hi some question about MMU table. background: 1.the CPU is ARM1176JS-Z. 2. L1 cache enabled 3.i want to enable MMU in bootloader...