Problems with interrupting LDM/STM Cortex M4?

I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions. The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr} The ICI bits...
Problems with interrupting LDM/STM Cortex M4?

I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions. The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr} The ICI bits...
LDM/STM interruption of Cortex-M7.

Hi Cortex-M7 specialists. I would like to know the Cortex-M7 behaviors when requested interrupts. In the Cortex-M3 case, LDM/STM and DIV will stop execution by interrupt requests (although those can be...
LDM/STM interruption of Cortex-M7.

Hi Cortex-M7 specialists. I would like to know the Cortex-M7 behaviors when requested interrupts. In the Cortex-M3 case, LDM/STM and DIV will stop execution by interrupt requests (although those can be...
AXI transaction when ldm/stm instruction used on cortex-a9

Note: This was originally posted on 15th September 2011 at http://forums.arm.com HI, ARM experts I used ldm/stm instruction to copy(read-write) memory with caches disabled. The code is listed as: int...