Atomic access LDR/STR vs LDREX/STREX

I'm working with the obsfucated RTL for Cortex-M3. I have a working design that muxes the 3 AHB-lite buses to 2 AXI3 buses. This design is analogous to the Xilinx designstart design with a code bus and...
About unsupported exclusive or atomic access issue

Hi, I am working on TI platform having 2 clusters of Cortex-A53 with 2 cores in each cluster. I am running TI provided Linux on cluster-0/core-0 with HYP mode software controlling stage-2 translation...
Atomic access LDR/STR vs LDREX/STREX

I'm working with the obsfucated RTL for Cortex-M3. I have a working design that muxes the 3 AHB-lite buses to 2 AXI3 buses. This design is analogous to the Xilinx designstart design with a code bus and...
About unsupported exclusive or atomic access issue

Hi, I am working on TI platform having 2 clusters of Cortex-A53 with 2 cores in each cluster. I am running TI provided Linux on cluster-0/core-0 with HYP mode software controlling stage-2 translation...
Are 128 bits atomic accesses possible with Cortex-A35?

Hi, I am using NXP i.MX 8X (Cortex-A35, i.e. ARMv8.0-A) and I would like to know if it is possible to make atomic 128 bits read/writes between 2 cores without a retry loop (Exclusive instructions)....