What is the difference between PoC and PoU for Cortex-A7 MPCore?

hi, experts: ARM ARM manual introduces a concept PoC and PoU for cache maintanance operations. Based on Cortex-A7 MPCore TRM and ARM ARM manual, i got below conclusion: 1. PoC points to external DRAM...
What is the difference between PoC and PoU for Cortex-A7 MPCore?

hi, experts: ARM ARM manual introduces a concept PoC and PoU for cache maintanance operations. Based on Cortex-A7 MPCore TRM and ARM ARM manual, i got below conclusion: 1. PoC points to external DRAM...
Cache type and cache operation sequence

I have a shared memory in DDR --- shared between two separate ARM execution environments (say A and B) in a heterogeneous compute SoC. SW on each execution units (A and B) Reads and Writes to this shared...
Cache type and cache operation sequence

I have a shared memory in DDR --- shared between two separate ARM execution environments (say A and B) in a heterogeneous compute SoC. SW on each execution units (A and B) Reads and Writes to this shared...
Store operations where the cache line is already cached (ACE protocol)

In Section C1.3 Channel Overview of the AMBA_AXI_and_ACE protocol specifications, It is mentioned under " Store operations where the cache line is already cache d" as : The initiating master component...