Cortex-A72 ACP deadlock issue

Can you share any examples of write access Cortex-A72 ACP port deadlocks? What are the limitations of using ACP ports at the system level, except for those mentioned in the A72 TRM manual
Deadlock accross multiple interconnects

Note: This was originally posted on 5th January 2011 at http://forums.arm.com For single AXI matrix, the interconnect can ensure that deadlock cannot occur via CDAS , however, could you please give me...
Signal deadlock in linting

Hello..I am doing linting for my RTL(AHB-SPMI) .I got Signal deadlock violation.Can anyone tell me what this deadlock signal is? and where it occurs?
Signal deadlock in linting

Hello..I am doing linting for my RTL(AHB-SPMI) .I got Signal deadlock violation.Can anyone tell me what this deadlock signal is? and where it occurs?
Deadlock accross multiple interconnects

Note: This was originally posted on 5th January 2011 at http://forums.arm.com For single AXI matrix, the interconnect can ensure that deadlock cannot occur via CDAS , however, could you please give me...