page table Cachability bit effect!

Hi experts, I really get confused with the page table cachability bit (c bit) effect (Cortex-A8) and need your help to find answer of my question. The questions is whether page table C-bit only controls...
page table Cachability bit effect!

Hi experts, I really get confused with the page table cachability bit (c bit) effect (Cortex-A8) and need your help to find answer of my question. The questions is whether page table C-bit only controls...
How to Isolate the cachelines with hardware failures in A72, L1,L2？

Hi，experts， if harware failures occures in L1 or L2 of A72，maybe，harware failures is Permanent。 if we can isolate the cachelines with hardware failures，CPU can work on。
How to Isolate the cachelines with hardware failures in A72, L1,L2？

Hi，experts， if harware failures occures in L1 or L2 of A72，maybe，harware failures is Permanent。 if we can isolate the cachelines with hardware failures，CPU can work on。
Inner/Outer share ability in Cortex R52

I am trying to configure memory attribute for cortex R52 in our SOC which is having integrated L1 I/D Cache and no coherent agent.and having system RAM. system is having two clusters with two cores...