CMN-700 Error Injection

Hi, I am trying to inject a SLC double-bit data ECC error with 'cmn_hns_err_inj' register in CMN-700. The detailed steps are as follows: 1. I chose the HN-F with LID 0 as the target point for error...
CMN-700 Error Injection

Hi, I am trying to inject a SLC double-bit data ECC error with 'cmn_hns_err_inj' register in CMN-700. The detailed steps are as follows: 1. I chose the HN-F with LID 0 as the target point for error...
L2 cache error injection and Prefetch Abort

Hello, I am using an ARM dual core Cortex A9 as part of our satellite computer SoC, and I am now trying to inject errors in the different cache levels of the CPU. In particular I am trying to trigger...
L2 cache error injection and Prefetch Abort

Hello, I am using an ARM dual core Cortex A9 as part of our satellite computer SoC, and I am now trying to inject errors in the different cache levels of the CPU. In particular I am trying to trigger...
Ecc error injection on Iram1 of Cortex-R5f

Hello all : Bacground: I am working on arm cortex-r5f , i want to inject 1/2bits ecc error in Iram1 . Specific: My m ost of the code is located in IRAM1 , but my injection error function code...