• Hotplug of secondary core
    After hotplug of secondary core, from where the execution start? What about peripheral register ie GIC register, are they resetted? Why and when hotplug required?
  • How do the TLB maintenance instructions affect other offline CPU cores disabled by CPU Hotplug in the kernel
    Hi, I'm a beginner in ARM architecture. 1) A re some TLBI instructions that can clean TLB entry for the Outer Shareable domain valid for other CPU cores that are offline? For example, if I make a...
  • As arm cortex R4 is a dual core processor, is there a concept of booting core (primary core) and secondary core?
    Cortex R4 processor architecture mentions the processor as dual core. Is there a concept of booting core(primary core) and secondary core? Please provide details on this aspect.
  • As arm cortex R4 is a dual core processor, is there a concept of booting core (primary core) and secondary core?
    Cortex R4 processor architecture mentions the processor as dual core. Is there a concept of booting core(primary core) and secondary core? Please provide details on this aspect.
  • How to compare ACPI states (Sx, Cx) with ARM Cortex-A processor states (Standby, Retention, Power Down, Dormant Mode, Hotplug, Stop, Deep Sleep) ?
    Hello, I'm a student and I'm interested in how to compare ACPI Sleep States (Sx) and processor power states (Cx) with ARM Cortex-A states e.g. Standby, Retention, Power Down, Dormant Mode, Hotplug, Stop...