Translation error at level1 in armv8 A72 cortex

Hi, I am trying to enable MMU on LS1046ARDB using baremetal boot code . We are translating 1GB of DRAM as NORMAL READ WRITE memory . We are able to load entries into translation tables successfully...
DRAM address mapping on a Cortex-A72 ARMv8

HI Everyone, I need help about DRAM address mapping on a Cortex A-72 especially my question is : given two physical memory addresses how can i know if they are in the same DIMM, Rank and Bank ? is there...
Translation error at level1 in armv8 A72 cortex

Hi, I am trying to enable MMU on LS1046ARDB using baremetal boot code . We are translating 1GB of DRAM as NORMAL READ WRITE memory . We are able to load entries into translation tables successfully...
DRAM address mapping on a Cortex-A72 ARMv8

HI Everyone, I need help about DRAM address mapping on a Cortex A-72 especially my question is : given two physical memory addresses how can i know if they are in the same DIMM, Rank and Bank ? is there...
Translation error in armv8 a72

Hello experts, I am trying to enable MMU on LS1046ARDB Board and have generated MMU translation table . I am able to write entries into translation table . I am running my code from flash memory and...