what is the Instruction L1 TLB and L2 TLB size?

if L1 TLB size = 32entry*64Byte = 2048 = 2k? L1 TLB cache line is 64Byte, becuse the entry size is 64 byte.I don't know if my understanding is correct.
what is the Instruction L1 TLB and L2 TLB size?

if L1 TLB size = 32entry*64Byte = 2048 = 2k? L1 TLB cache line is 64Byte, becuse the entry size is 64 byte.I don't know if my understanding is correct.
TLB translate

i want to know why the application point to flash, what is the scenario？ why does not OS point to RAM
TLB translate

i want to know why the application point to flash, what is the scenario？ why does not OS point to RAM
TLB stage2 translation

hi,all.I am working to implement 2 level TLB ,and i notice that the TLB have stage 2 translation when at no secure EL0 and EL1 translation regime。but i doubt if i also need to implement stage2 in 2 level...