Multi core L1 cache coherent

Dear experts, I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation. Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached)...
Multi core L1 cache coherent

Dear experts, I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation. Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached)...
Does Cortex-M7 support SMP?

Does Cortex-M7 support SMP? I'm plan to start project using ARM core. So I'm searching for which core is suitable. I want to use a core that is as small as possible. I'd like to use little kernel...
SMP ARM cores hang when using DMA and two cores enabled

Hi, I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA. I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode. SOC used is Altera Cyclone...
SMP ARM cores hang when using DMA and two cores enabled

Hi, I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA. I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode. SOC used is Altera Cyclone...