Why does ARM Branch with Link (BL) instruction considers prefetch?

Hi, When I read the words below dot line, I don't understand why "R14 is adjusted to allow for the prefetch" Could you explain it to me? Thanks, ....... Branch with Link (BL) writes the old PC into the...
Why does ARM Branch with Link (BL) instruction considers prefetch?

Hi, When I read the words below dot line, I don't understand why "R14 is adjusted to allow for the prefetch" Could you explain it to me? Thanks, ....... Branch with Link (BL) writes the old PC into the...
How do branch instructions influence the performance of Cortex-A77?

In "Arm Cortex-A77 Core Software Optimization Guide", it says: In my understanding, it would be very difficult to predict multiple branch instructions in a 32-Byte aligned instruction memory...
How do branch instructions influence the performance of Cortex-A77?

In "Arm Cortex-A77 Core Software Optimization Guide", it says: In my understanding, it would be very difficult to predict multiple branch instructions in a 32-Byte aligned instruction memory...
MMU deactivation and I-Cache / Branch Predictor

Hi ! In order to call some functionality hard-coded in my board ROM (HAB from NXP i.MX6 board), I need to shut down the MMU: the ROM is not position independent. In particular, it is not always possible...