Cortex-A53 direct access to cache: How are instructions encoded in the L1 I-cache?

The TRM for the Cortex-A53 has a section on direct access to various internal memories, including the L1 I-cache and D-caches. I'm successfully able to dump both tag and data for the I-cache and D-cache...
Cortex-A53 direct access to cache: How are instructions encoded in the L1 I-cache?

The TRM for the Cortex-A53 has a section on direct access to various internal memories, including the L1 I-cache and D-caches. I'm successfully able to dump both tag and data for the I-cache and D-cache...
Cortex-R52 data cache content

Hi everyone, Is there a way to read the data cache content? I'm using Xilinx SoC ZCU102 evaluation board. Thanks
Cortex-R52 data cache content

Hi everyone, Is there a way to read the data cache content? I'm using Xilinx SoC ZCU102 evaluation board. Thanks
Cortex A-35 cache L2 content access

Hi, I'm currently working on an SCO (i.MX8QXP from NXP) containing an A-35 cluster (4 cores) with a L2 cache. Is there anyway to access the content of the L2 cache? Our current debugger, Trace32,...