Intercore interrupts on a53 between EL1 and EL3

We are working on Xilinx MPSOC which has 4 A53 cores, We are trying to run Linux(EL1) on 3 cores and Freertos(EL3) on 4th core. When software generated interrupts are raised from Linux , Freertos is not...
Intercore interrupts on a53 between EL1 and EL3

We are working on Xilinx MPSOC which has 4 A53 cores, We are trying to run Linux(EL1) on 3 cores and Freertos(EL3) on 4th core. When software generated interrupts are raised from Linux , Freertos is not...
Transition from EL3 to EL1 on A53

I have a standalone app running at EL3 in OCM on an A53 processor. The code boots from flash. I load an elf image into RAM and need to transition to its entry point running at EL1. I try and make the...
Transition from EL3 to EL1 on A53

I have a standalone app running at EL3 in OCM on an A53 processor. The code boots from flash. I load an elf image into RAM and need to transition to its entry point running at EL1. I try and make the...
ARMv8 : How Cache Handling at EL3 is different to that of Cache handling in EL1 (NS=0)?

Scenario: Sent a buffer reference and its size from EL1 secure world as a SIP SMC , such that EL3 write on that buffer and ERET to EL1. Query: 1. Does cache flush is required at any exception...