Is it possible to read the raw L1/L2 cache data and tag bits on the Cortex-A9?

I've been digging through the Technical Reference Manual (TRM) for the Cortex-A9 and so far it seems that it's possible to gather data about events such as hit and miss rates, but there doesn't seem to...
Is it possible to read the raw L1/L2 cache data and tag bits on the Cortex-A9?

I've been digging through the Technical Reference Manual (TRM) for the Cortex-A9 and so far it seems that it's possible to gather data about events such as hit and miss rates, but there doesn't seem to...
reading 8 bit data through single bit variable

someone has worked on this, kindly let me know, how do we pass a 32 bit word to a variable declared as 'sbit', i tried this way, AND with 0x80 (1000 0000) and get 1 bit at a time, this seems to work...
reading 8 bit data through single bit variable

someone has worked on this, kindly let me know, how do we pass a 32 bit word to a variable declared as 'sbit', i tried this way, AND with 0x80 (1000 0000) and get 1 bit at a time, this seems to work...
How to map tag RAM banks to data cache lines in Cortex-R5?

Hi, We are using Cortex-R5F. Through the AXI slave interface, we are accessing the data cache data RAM, tag RAM and dirty RAM. We would like to know how we can associate the bits found in the data...