SLVERR from L3 not raised in ISR of ARM PL310 L2 cache controller

Hello, I am trying to raise L3 SLV interrupts of the ARM PL310 L2 cache controller by generating an AXI slave error on a L2C slave peripheral (which is not DDRC). On my Xilinx Zynq SoC, the ARM PL310...
SLVERR from L3 not raised in ISR of ARM PL310 L2 cache controller

Hello, I am trying to raise L3 SLV interrupts of the ARM PL310 L2 cache controller by generating an AXI slave error on a L2C slave peripheral (which is not DDRC). On my Xilinx Zynq SoC, the ARM PL310...
PL310 cache synchronization

Hi ! I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation. - when I want to perform a synchronization, should I just wait for bit 0 (bit...
PL310 cache synchronization

Hi ! I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation. - when I want to perform a synchronization, should I just wait for bit 0 (bit...
L2 Cache(Pl310) initialisation sequence

Hi , I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core. Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn...