On Cortex-M7, can speculative access bring accessed data to D cache?

Asking this to better understand how to manage cache consistency on I/O buffer for DMA read. Is it possible that in between of cache invalidation on the buffer and end of DMA read, a speculative data...
On Cortex-M7, can speculative access bring accessed data to D cache?

Asking this to better understand how to manage cache consistency on I/O buffer for DMA read. Is it possible that in between of cache invalidation on the buffer and end of DMA read, a speculative data...
Speculative execution/loads on Cortex-A5

Hello. I just found some information about speculative execution and speculative loads/cache line-fills on some ARM processors. Unfortunately I wasn't able to find if any of these present on Cortex-A5...
Speculative execution/loads on Cortex-A5

Hello. I just found some information about speculative execution and speculative loads/cache line-fills on some ARM processors. Unfortunately I wasn't able to find if any of these present on Cortex-A5...
Cortex-A9 Branch prediction to speculative execution

Hi, I am building a cycle accurate simulator for the Cortex-A9 core, and so far I constructed most of the stages of the pipeline. However I am having trouble placing something that is not clear in any...