Cortex M7 cache ECC error

Hi, I'm currently working on STM32H7 which run a cortex M7. I'm trying to figure out how an ECC error upon a look up in the instruction or data cache is reported to the core. The only mention I've...
Cortex M7 cache ECC error

Hi, I'm currently working on STM32H7 which run a cortex M7. I'm trying to figure out how an ECC error upon a look up in the instruction or data cache is reported to the core. The only mention I've...
Cache ECC in Cortex-R5 & Event bus

Hi everybody, I am using a Cortex-R5 embedded in a TMS570LC4357, and I am wondering to use the cache configuration as "Do not generate Aborts, force write through, enable hardware recovery". As far...
Cache ECC in Cortex-R5 & Event bus

Hi everybody, I am using a Cortex-R5 embedded in a TMS570LC4357, and I am wondering to use the cache configuration as "Do not generate Aborts, force write through, enable hardware recovery". As far...
ATCM ECC error causes prefetch abort despite ECC check being disabled.

Hello, I am working with TI's TMS570LS3137 (ARM Cortex R4F). A certain part of my code consistently causes a prefetch abort (I say part because the exact location seems to vary slightly). To try...