gnu GCC option to enforce 8-byte stack alignment (necessary for R52)?

Hello, ARM support and R52 TRM have indicated that the R52 core requires maintaining an 8-byte aligned Stack (meaning compiler shall always push/pop registers in even numbers), and I see in my current...
gnu GCC option to enforce 8-byte stack alignment (necessary for R52)?

Hello, ARM support and R52 TRM have indicated that the R52 core requires maintaining an 8-byte aligned Stack (meaning compiler shall always push/pop registers in even numbers), and I see in my current...
Memory alignment while using LDR instruction in cortex A9

Note: This was originally posted on 3rd August 2012 at http://forums.arm.com Hi, I am facing some problem while trying to load a 32 bit value into a register by using LDR R0 [R1] where R1 is a pointer...
Memory alignment while using LDR instruction in cortex A9

Note: This was originally posted on 3rd August 2012 at http://forums.arm.com Hi, I am facing some problem while trying to load a 32 bit value into a register by using LDR R0 [R1] where R1 is a pointer...
Compiler options for Cortex-R52 CoreMark

Hi, From https://developer.arm.com/Processors/Cortex-R52, the CoreMark performance score for Cortex-R52 is 4.3 CoreMark/MHz. Would you mind sharing the compiler version and the whole compiler options...