How to do cache invalid on Cortex-A53?

hi, I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid. Could you give me any suggestion about cache invalid? Thanks! ...
How to do cache invalid on Cortex-A53?

hi, I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid. Could you give me any suggestion about cache invalid? Thanks! ...
Cortex-A53 L2 cache invalidation

Is it possible to invalidate by software the L2 cache in Cortex-A53? My code is currently too small to produce cache misses in the L2 cache so that I would like to simulate L2 cache misses by invalidating...
Cortex-A53 L2 cache invalidation

Is it possible to invalidate by software the L2 cache in Cortex-A53? My code is currently too small to produce cache misses in the L2 cache so that I would like to simulate L2 cache misses by invalidating...
L1 Cache Eviction Corrupting DDR on A9

Hi All! I am working with a Xilinx Zynq 7000 SoC which uses the Cortex A9 as a CPU. I've observed a problem wherein a section of memory marked strongly-ordered and non-cacheable (0xc02) in the MMU table...