Cortex-A53 - Understanding Translation Table (Cannot enable MMU)

Hello, I'm trying to get MMU working on Cortex-A53. But still fails since at least 3 days. :( I created following tables: Level 1 0 0000000010006003 1 0000000010007003 2 0000000010008003...
Cortex-A53 - Understanding Translation Table (Cannot enable MMU)

Hello, I'm trying to get MMU working on Cortex-A53. But still fails since at least 3 days. :( I created following tables: Level 1 0 0000000010006003 1 0000000010007003 2 0000000010008003...
On Chip RAM is slow after enabling MMU, and using external ram aborts

Hello All, I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU. Issue 1: But what I could notice is code region in external ram is executing faster than internal...
On Chip RAM is slow after enabling MMU, and using external ram aborts

Hello All, I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU. Issue 1: But what I could notice is code region in external ram is executing faster than internal...
Enabling MMU crashes ARM Cortex A7

I am working on smp_prime code of ARM - A9. And a i want to use that code for cortex A7. But after making changes like setting smp bit in ACTLR, Making the memory region device and non coherent- then...