ARMv7 vs. Cortex-A9 TRM MPIDR register

Note: This was originally posted on 8th May 2013 at http://forums.arm.com Hello, why do the Multiprocessor Affinity Register (MPIDR) definitions in the ARMv7 Architecture Reference (e.g. ARM DDI 0406C...
CPUACTLR_EL1 and S3_1_C15_C2_0 in Cortex-A57 TRM

hi, experts: In Cortex-A57 TRM chapter 4.3.66 : It defines CPUACTLR_EL1 register, but this register name is not CPUACTLR_EL1. Its name is S3_1_C15_C2_0. Why? best wishes, hi
ARMv7 vs. Cortex-A9 TRM MPIDR register

Note: This was originally posted on 8th May 2013 at http://forums.arm.com Hello, why do the Multiprocessor Affinity Register (MPIDR) definitions in the ARMv7 Architecture Reference (e.g. ARM DDI 0406C...
CPUACTLR_EL1 and S3_1_C15_C2_0 in Cortex-A57 TRM

hi, experts: In Cortex-A57 TRM chapter 4.3.66 : It defines CPUACTLR_EL1 register, but this register name is not CPUACTLR_EL1. Its name is S3_1_C15_C2_0. Why? best wishes, hi
Normal/Non-shareable/Non-cacheable memory note on Cortex-A5 TRM

Does anyone know what means "Does not access L1 caches." note in the "Treatment of memory attributes" table from [1] for Normal/Non-shareable/Non-cacheable memory for Cortex-A5? Thank you! [1] infocenter...