AHB Lite Multiple burst without idle transfer

Hi All, Consider the following burst transfers. 1. INCR4 (WR) IDLE INCR4(RD) 2. INCR4 (WR) INCR4(RD) 3. INCR4 (WR - WR1 ,WR2, IDLE, WR3 ,WR4 ) INCR4(RD) All the above transactions are valid...
AHB Lite Multiple burst without idle transfer

Hi All, Consider the following burst transfers. 1. INCR4 (WR) IDLE INCR4(RD) 2. INCR4 (WR) INCR4(RD) 3. INCR4 (WR - WR1 ,WR2, IDLE, WR3 ,WR4 ) INCR4(RD) All the above transactions are valid...
early burst termination - ahb - interconnect

the system have 2 masters - M0,M1, and 2 slaves- S0, S1. M0 transmit to S0, INCR4 : NON,SEQ and then early burst termination and M1 transmit to S1 new burst. In that clock cycle what S0 expects to see...
Multi-layer AHB-Lite - Handling of HREADY for back-to-back transfers from different managers

Dear ARM community, I'm implementing a multi-layer AHB-Lite system based on dvi0045 and have some doubts about the handling of HREADY. TL;DR : Is it possible to interleave transfers of different AHB...
Burst termination with BUSY on AHB Lite

Hello, I have some question when Master used "Undefined Length" and termination with BUSY, the following is my waveform : My question is : 1) When T5-T6, Slave still on address phase? 2) When...