Atomic access LDR/STR vs LDREX/STREX

I'm working with the obsfucated RTL for Cortex-M3. I have a working design that muxes the 3 AHB-lite buses to 2 AXI3 buses. This design is analogous to the Xilinx designstart design with a code bus and...
Atomic access LDR/STR vs LDREX/STREX

I'm working with the obsfucated RTL for Cortex-M3. I have a working design that muxes the 3 AHB-lite buses to 2 AXI3 buses. This design is analogous to the Xilinx designstart design with a code bus and...
Understanding interrupt latency and jitter in Cortex-M

Hi, I've been trying to get a good grasp of the variables associated with interrupt handling in the Cortex-M family. I've read " A Beginner’s Guide on Interrupt Latency - and Interrupt Latency of the...
Understanding interrupt latency and jitter in Cortex-M

Hi, I've been trying to get a good grasp of the variables associated with interrupt handling in the Cortex-M family. I've read " A Beginner’s Guide on Interrupt Latency - and Interrupt Latency of the...
Memory alignment while using LDR instruction in cortex A9

Note: This was originally posted on 3rd August 2012 at http://forums.arm.com Hi, I am facing some problem while trying to load a 32 bit value into a register by using LDR R0 [R1] where R1 is a pointer...