[Cortex-A53] STP instruction stores out of the specified memory

Hi Experts， I have a question about "STP" instruction in Cortex-A53. STP W6, W6, [SP, #20] --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted. I don't know why cause it....
[Cortex-A53] STP instruction stores out of the specified memory

Hi Experts， I have a question about "STP" instruction in Cortex-A53. STP W6, W6, [SP, #20] --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted. I don't know why cause it....
c5, Instruction Fault Status Register

Note: This was originally posted on 5th January 2012 at http://forums.arm.com I have implemented a MMU logic for the Cortex A8 on the BeagleBoard. It seems to work well. But after handling the first data...
c5, Instruction Fault Status Register

Note: This was originally posted on 5th January 2012 at http://forums.arm.com I have implemented a MMU logic for the Cortex A8 on the BeagleBoard. It seems to work well. But after handling the first data...
Converting virtual address of Instruction fault address register to physical address in cotex A9

Content of IFAR=0xaa4e8ef0 IFSR=0x0000000d DFSR:0x00000000 DFAR:0x00004000 How to find Physical address form this?