ARM Bootloader: flush D/I-cache, disable D-cache and enable I-cache

Hello everyone, I'm analysing u-boot for s3c2440(arm920t), and at the first stage u-boot does something like this: mov R0, #0 mcr P15, 0, R0, C7, C7, 0 ; flush v3/v4 caches mcr P15, 0, R0, C8...
ARM Bootloader: flush D/I-cache, disable D-cache and enable I-cache

Hello everyone, I'm analysing u-boot for s3c2440(arm920t), and at the first stage u-boot does something like this: mov R0, #0 mcr P15, 0, R0, C7, C7, 0 ; flush v3/v4 caches mcr P15, 0, R0, C8...
How to add nRF5 SDK pathes to system-wide Keil settings?

Hello, After I extracted nRF5 SDK to some location, how do I add that directory (with all subdirs) to Keil settings, so I don't have to add each subdirectory manually to each newly created project?...
How to add nRF5 SDK pathes to system-wide Keil settings?

Hello, After I extracted nRF5 SDK to some location, how do I add that directory (with all subdirs) to Keil settings, so I don't have to add each subdirectory manually to each newly created project?...
ARM Cortex A9 flush cache

I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements. Is it doable from user mode? Processor: ARM Cortex...