the width of AXI ID conflict

Hi： I have an idea that A15 and R7 are located on different AXI buses to build two systems respectively. In order to be more flexible, I hope to connect the two systems so that they can access each...
the width of AXI ID conflict

Hi： I have an idea that A15 and R7 are located on different AXI buses to build two systems respectively. In order to be more flexible, I hope to connect the two systems so that they can access each...
AXI fixed burst to a slave with narrow data width

Hi, I have an AXI master with data width 64, and an AHB slave of data width 32. What would happen when there is a 64bit FIXED burst READ (i.e., asize=3 )to an address 0X100 of the slave? Would the...
AXI fixed burst to a slave with narrow data width

Hi, I have an AXI master with data width 64, and an AHB slave of data width 32. What would happen when there is a 64bit FIXED burst READ (i.e., asize=3 )to an address 0X100 of the slave? Would the...
LL/SC exclusive access by register width or cache line width?

Note: This was originally posted on 30th May 2012 at http://forums.arm.com Hi. I'm working on the next release of my lock-free data structure library. I'm using LL/SC on ARM. To use LL/SC as LL/SC (rather...