Are 128 bits atomic accesses possible with Cortex-A35?

Hi, I am using NXP i.MX 8X (Cortex-A35, i.e. ARMv8.0-A) and I would like to know if it is possible to make atomic 128 bits read/writes between 2 cores without a retry loop (Exclusive instructions)....
Are 128 bits atomic accesses possible with Cortex-A35?

Hi, I am using NXP i.MX 8X (Cortex-A35, i.e. ARMv8.0-A) and I would like to know if it is possible to make atomic 128 bits read/writes between 2 cores without a retry loop (Exclusive instructions)....
Performance ratio between A35 and M4

I am working on project and i used A35 to measure the performance of Application and this application will be ported on M4 , is there a fixed ratio or an equation so i can estimate the execution time...
Performance ratio between A35 and M4

I am working on project and i used A35 to measure the performance of Application and this application will be ported on M4 , is there a fixed ratio or an equation so i can estimate the execution time...
Cortex-A35 Counter-timer Physical Count register (CNTPCT_EL0) always reads zero

Counter-timer Physical Count register CNTPCT_EL0 always reads zero on FVP_Base_Cortex-A35x1. I expect the value of this register to change over time. I set $CNTFRQ_EL0=35000000, and $CNTP_CTL_EL0...